CERN Accelerating science

VeloPix, a new hybrid pixel readout ASIC for the upgrade of the VELO detector of LHCb.

by Jan Buytaert

The LHCb-VELO group, which is composed of several institutes from the UK, Spain, Netherlands, Russia, Brazil and CERN are constructing an upgraded version of the VErtex LOcator (VELO) to be installed and commissioned during the long shutdown LS2 in 2019/2020.

Unlike the currently operating strip detector, which enters its final year of very successful operation and has truly performed beyond expectation, it will be a pixel based detector made of nearly 41 million small square (55um x 55um) sensing elements. This change is mandated by the requirement to perform pattern recognition at 40 MHz in a full software trigger and to cope with a 5 fold increase in luminosity. The new pixel detector will also approach the LHC colliding beams by an unprecedented 5 mm. 

To design a new readout ASIC called VeloPix, LHCb has benefited enormously from the vast experience of the Medipix/Timepix design team of the CERN and Nikhef micro-electronics groups. The development of the “Timepix3” ASIC, in which LHCb has actively participated, already demonstrated several of the new concepts required for the final VeloPix. Because space inside a pixel is very limited and one wants to add as much functionality as possible, a new approach with so-called logic super-pixel groups has been implemented, where pixels share common functionality such as time tagging, hit buffering and readout control. Also a new data driven readout was introduced, which means that as soon as a pixel was hit by a particle, a small data packet would be created and flow off chip without further traffic control.

For VeloPix a major challenge remained, namely a further tenfold increase in total data rate while limiting the power consumption. This was solved by implementing four multi-gigabit/sec serial outputs on the ASIC, providing a sustained output rate of nearly 20 Gigabit/s. The complete detector consists of 624 ASICs delivering a sustained data rate of nearly 2 Terabit/s over 1020 optical links to an online computing farm. Finally, the very high radiation environment and vacuum in which it will operate are factors further adding to the complexity of this ASIC. 

A first ASIC was submitted for fabrication in 2016 and has been extensively tested. Some errors, such as single event latch-up, appeared unexpectedly and were identified and they were understood as a consequence of a recent change of ASIC manufacturer. Also, the excessive clock jitter degraded significantly the quality of the serial data transmission. A new fabrication technique, which successfully addressed these issues, was launched in 2017 and all silicon wafers have successfully been tested in a wafer probe station. The dies are now being thinned and bump bonded to the sensors. The construction of the detector modules will start this summer, in time for completion and installation of the full detector in a year from now.   


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